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19-2543; Rev 0; 7/02
Dual 1:5 Differential Clock Drivers with LVPECL Inputs and LVDS Outputs
General Description
The MAX9317/MAX9317A/MAX9317B/MAX9317C lowskew, dual 1-to-5 differential drivers are designed for clock and data distribution. The differential input is reproduced at five LVDS outputs with a low output-tooutput skew of 5ps. The MAX9317/MAX9317A are designed for low-voltage operation from a 2.375V to 2.625V power supply for use in 2.5V systems. The MAX9317B/MAX9317C operate from a 3.0V to 3.6V power supply for use in 3.3V systems. The MAX9317A/MAX9317C feature 50 input termination resistors to reduce component count. The MAX9317 family is available in 32-pin 7mm 7mm TQFP and space-saving 5mm 5mm QFN packages and operate across the extended temperature range of -40C to +85C. The MAX9317A is pin compatible with ON Semiconductor's MC100EP210S. o 145ps (max) Part-to-Part Skew o 5ps Output-to-Output Skew o 330ps Propagation Delay from CLK_ to Q_ o 2.375V to 2.625V Operation (MAX9317/MAX9317A) o 3.0V to 3.6V Operation (MAX9317B/MAX9317C) o ESD Protection: 2kV (Human Body Model) o Internal 50 Input Termination Resistors (MAX9317A/MAX9317C)
Features
o Guaranteed 1.0GHz Operating Frequency
MAX9317/MAX9317A/MAX9317B/MAX9317C
Ordering Information
PART TEMP RANGE PINPACKAGE NOMINAL SUPPLY VOLTAGE (V) 2.5 2.5 2.5 2.5 3.3 3.3 3.3 3.3
Applications
Precision Clock Distribution Low-Jitter Data Repeaters Data and Clock Drivers and Buffers Central-Office Backplane Clock Distribution DSLAM Backplanes Base Stations ATE
Pin Configurations appear at end of data sheet.
MAX9317ETJ* -40C to +85C 32 Thin QFN MAX9317ECJ -40C to +85C 32 TQFP MAX9317AETJ* -40C to +85C 32 Thin QFN MAX9317AECJ -40C to +85C 32 TQFP MAX9317BETJ* -40C to +85C 32 Thin QFN MAX9317BECJ -40C to +85C 32 TQFP MAX9317CETJ* -40C to +85C 32 Thin QFN MAX9317CECJ -40C to +85C 32 TQFP *Future product--contact factory for availability.
Functional Diagram
QA0 QA0 QA1 QA1 QA2 27 31 30 29 28 26 QA2 MAX9317 MAX9317A MAX9317B MAX9317C 24 23 CLKA CLKA CLKB CLKB 3 4 6 7 22 21 20 19 18 RIN 50 VTB GND 5 1, 8 10 11 12 13 14 15 RIN 50 17 QA3 QA3 QA4 QA4 QB0 QB0 QB1 QB1 QB2
VCC VTA
9, 16 25, 32 2 RIN 50 RIN 50
QB4
QB4
QB3
QB3
MAX9317A/MAX9317C ONLY.
________________________________________________________________ Maxim Integrated Products
QB2
1
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Dual 1:5 Differential Clock Drivers with LVPECL Inputs and LVDS Outputs MAX9317/MAX9317A/MAX9317B/MAX9317C
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.1V Input Pins to GND.......................................-0.3V to (VCC + 0.3V) Differential Input Voltage .............VCC or 3.0V, whichever is less Continuous Output Current .................................................28mA Surge Output Current..........................................................50mA Continuous Power Dissipation (TA = +70C) 32-Pin, 7mm 7mm TQFP (derate 20.7mW/C above +70C) .................................1.65W 32-Pin 5mm 5mm QFN (derate 21.3mW/C above +70C) ...................................1.7W Junction-to-Ambient Thermal Resistance in Still Air 32-Pin, 7mm 7mm TQFP......................................+48.4C/W 32-Pin, 5mm 5mm QFN ..........................................+47C/W Junction-to-Case Thermal Resistance 32-Pin, 7mm 7mm TQFP.........................................+12C/W 32-Pin, 5mm 5mm QFN ............................................+2C/W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (CLK_, CLK_, Q_, Q_, VT_) .............2kV Soldering Temperature (10s) ...........................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 2.375V to 2.625V (MAX9317/MAX9317A), VCC = 3.0V to 3.6V (MAX9317B/MAX9317C), all outputs loaded 100 1% between Q_ and Q_, unless otherwise noted. Typical values are at V CC = 2.5V (MAX9317/MAX9317A), V CC = 3.3V (MAX9317B/MAX9317C), VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, and 3)
PARAMETER SYMBOL CONDITIONS -40C MIN TYP MAX MIN +25C TYP MAX MIN +85C TYP MAX UNITS
INPUTS (CLK_, CLK_) Differential Input High Voltage Differential Input Low Voltage VIHD VILD Figure 1 Figure 1 MAX9317/ MAX9317A MAX9317B/ MAX9317C 1.2 0 0.1 0.1 VCC VCC - 0.1 VCC 3.0 1.2 0 0.1 0.1 VCC VCC - 0.1 VCC 3.0 1.2 0 0.1 0.1 VCC VCC - 0.1 VCC V 3.0 V V
Differential Input Voltage
VID
VIHD VILD
Input Current Input Termination Resistance OUTPUTS (Q_, Q_) Output High Voltage Output Low Voltage
IIH, IIL
CLK_, or CLK_ = VIHD or VILD, MAX9317/MAX9317B MAX9317A/MAX9317C, Figure 2 (Note 4)
-60
+60
-60
+60
-60
+60
A
RIN
43
50
57
43
50
57
43
50
57
VOH VOL
Figure 1 Figure 1 0.9
1.6 0.9
1.6 0.9
1.6
V V
2
_______________________________________________________________________________________
Dual 1:5 Differential Clock Drivers with LVPECL Inputs and LVDS Outputs
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.375V to 2.625V (MAX9317/MAX9317A), VCC = 3.0V to 3.6V (MAX9317B/MAX9317C), all outputs loaded 100 1% between Q_ and Q_, unless otherwise noted. Typical values are at V CC = 2.5V (MAX9317/MAX9317A), V CC = 3.3V (MAX9317B/MAX9317C), VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1, 2, and 3)
PARAMETER Differential Output Voltage Change in VOD Between Complementary Output States Output Offset Voltage Change in VOS Between Complementary Output States Output ShortCircuit Current POWER SUPPLY Power-Supply Current (Note 5) ICC MAX9317/9317A MAX9317B/9317C 69 75 107 107 75 81 107 107 80 86 107 107 mA SYMBOL VOD CONDITIONS Figure 1 -40C MIN 250 TYP 350 MAX 450 MIN 250 +25C TYP 350 MAX 450 MIN 250 +85C TYP 350 MAX 450 UNITS mV
MAX9317/MAX9317A/MAX9317B/MAX9317C
VOD
7
50
6
50
6
50
mV
VOS
1.125 1.25 1.375 1.125 1.25 1.375 1.125 1.25 1.375
V
VOS Q_ shorted to Q_ IOSC Q_ or Q_ shorted to GND
25
25
25
mV
12 28
12 28
12 28 mA
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.375V to 2.625V (MAX9317/MAX9317A) or VCC = 3.0V to 3.6V (MAX9317B/MAX9317C), all outputs loaded with 100 1%, between Q_ and Q_, fIN 1.0GHz, input transition time = 125ps (20% to 80%), VIHD - VILD = 0.15V to VCC, unless otherwise noted. Typical values are at VCC = 2.5V (MAX9317/MAX9317A), VCC = 3.3V (MAX9317B/MAX9317C), fIN = 1.0GHz, VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1 and 4)
PARAMETER Propagation Delay CLK_, CLK_ to Q_, Q_ Output-to-Output Skew Part-to-Part Skew Added Random Jitter Added Deterministic Jitter Operating Frequency SYMBOL tPHL tPLH tSKEW1 tSKEW2 tRJ tDJ fMAX CONDITIONS -40C MIN 250 TYP 310 MAX 600 MIN 250 +25C TYP 330 MAX 600 MIN 250 +85C TYP 335 MAX 600 UNITS
Figure 1
ps
(Note 6) (Note 7) fIN = 1.0GHz, clock pattern (Note 8) fIN = 1.0GHz, 223 - 1 PRBS pattern (Note 8) VOD 250mV 1.0
9
55 145
5
45 145
4
25 145
ps ps ps(RMS) ps(P-P) GHz
0.8 80
2.0 105 1.0
0.8 80
2.0 105 1.0
0.8 80
2.0 105
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3
Dual 1:5 Differential Clock Drivers with LVPECL Inputs and LVDS Outputs MAX9317/MAX9317A/MAX9317B/MAX9317C
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.375V to 2.625V (MAX9317/MAX9317A) or VCC = 3.0V to 3.6V (MAX9317B/MAX9317C), all outputs loaded with 100 1%, between Q_ and Q_, fIN 1.0GHz, input transition time = 125ps (20% to 80%), VIHD - VILD = 0.15V to VCC, unless otherwise noted. Typical values are at VCC = 2.5V (MAX9317/MAX9317A), VCC = 3.3V (MAX9317B/MAX9317C), fIN = 1.0GHz, VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.) (Notes 1 and 4)
PARAMETER Differential Output Rise/Fall Time SYMBOL CONDITIONS -40C MIN 140 TYP 200 MAX 300 MIN 140 +25C TYP 205 MAX 300 MIN 140 +85C TYP 205 MAX 300 UNITS
tR/tF
20% to 80%, Figure 1
ps
Note 1: Measurements are made with the device in thermal equilibrium. Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. Note 3: DC parameters are production tested at +25C. DC limits are guaranteed by design and characterization over the full operating temperature range. Note 4: Guaranteed by design and characterization, and are not production tested. Limits are set to 6 sigma. Note 5: All outputs loaded with 100 differential, all inputs biased differential high or low except VT_. Note 6: Measured between outputs of the same device at the signal crossing points for a same-edge transition. Note 7: Measured between outputs on different devices for identical transitions and VCC levels. Note 8: Device jitter added to the input signal.
Typical Operating Characteristics
(MAX9317, VCC = 2.5V, all outputs loaded with 100 1%, between Q_ and Q_, fIN = 1.0GHz, input transition time = 125ps (20% to 80%), VIHD = VCC - 1.0V, VILD = VCC - 1.5V, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX9317 toc01
OUTPUT AMPLITUDE (VOH - VOL) vs. CLK_ FREQUENCY
MAX9317 toc02
OUTPUT RISE/FALL TIME vs. TEMPERATURE
MAX9317 toc03
90 INPUTS OPEN, OUTPUTS TERMINATED WITH 100 DIFFERENTIAL 85 SUPPLY CURRENT (mA)
400
230
300
OUTPUT RISE/FALL TIME (ps)
OUTPUT AMPLITUDE (mV)
220 FALL TIME
80
210
200
75
200 RISE TIME 190
70
100
65 -40 -15 10 35 TEMPERATURE (C) 60 85
0 0 0.5 1.0 1.5 CLK_ FREQUENCY (GHz) 2.0
180 -40 -15 10 35 TEMPERATURE (C) 60 85
CLK-TO-Q PROPAGATION DELAY vs. TEMPERATURE
MAX9317 toc04
CLK-TO-Q PROPAGATION DELAY vs. HIGH VOLTAGE OF DIFFERENTIAL INPUT (VIHD)
CLK-TO-Q PROPAGATION DELAY (ps)
MAX9317 toc05
340 CLK-TO-Q PROPAGATION DELAY (ps) 335 330 325 320 315 310 -40 -15 tPHL
324.0
323.5 tPHL 323.0 tPLH 322.5
tPLH
322.0 10 35 TEMPERATURE (C) 60 85 1.2 1.5 1.8 2.1 2.4 HIGH VOLTAGE OF DIFFERENTIAL INPUT (V)
4
_______________________________________________________________________________________
Dual 1:5 Differential Clock Drivers with LVPECL Inputs and LVDS Outputs
Pin Description
NAME PIN 1, 8 MAX9317 MAX9317B GND N.C. 2 -- CLKA CLKA N.C. 5 -- CLKB CLKB VCC QB4 QB4 QB3 QB3 QB2 QB2 QB1 QB1 QB0 QB0 QA4 QA4 QA3 QA3 QA2 QA2 QA1 QA1 QA0 QA0 EP MAX9317A MAX9317C GND -- VTA CLKA CLKA -- VTB CLKB CLKB VCC QB4 QB4 QB3 QB3 QB2 QB2 QB1 QB1 QB0 QB0 QA4 QA4 QA3 QA3 QA2 QA2 QA1 QA1 QA0 QA0 EP FUNCTION Ground No Connection. Connect this pin to ground or leave floating. CLKA Input Termination Voltage. This pin is connected to CLKA and CLKA through 50 termination resistors. Connect this pin to VCC - 2V for an LVPECL input signal on CLKA or leave floating for an LVDS input signal. Noninverting Differential Clock Input A Inverting Differential Clock Input A No Connection. Connect this pin to ground or leave floating. CLKB Input Termination Voltage. This pin is connected to CLKB and CLKB through 50 termination resistors. Connect this pin to VCC - 2V for an LVPECL input signal on CLKB or leave floating for an LVDS input signal. Noninverting Differential Clock Input B Inverting Differential Clock Input B Positive Supply Voltage. Bypass each VCC pin to ground with 0.1F and 0.01F ceramic capacitors. Place the capacitors as close to the device as possible with the 0.01F capacitor closest to the device. CLKB Inverting Differential Output 4. Terminate with 100 to QB4. CLKB Noninverting Differential Output 4. Terminate with 100 to QB4. CLKB Inverting Differential Output 3. Terminate with 100 to QB3. CLKB Noninverting Differential Output 3. Terminate with 100 to QB3. CLKB Inverting Differential Output 2. Terminate with 100 to QB2. CLKB Noninverting Differential Output 2. Terminate with 100 to QB2. CLKB Inverting Differential Output 1. Terminate with 100 to QB1. CLKB Noninverting Differential Output 1. Terminate with 100 to QB1. CLKB Inverting Differential Output 0. Terminate with 100 to QB0. CLKB Noninverting Differential Output 0. Terminate with 100 to QB0. CLKA Inverting Differential Output 4. Terminate with 100 to QA4. CLKA Noninverting Differential Output 4. Terminate with 100 to QA4. CLKA Inverting Differential Output 3. Terminate with 100 to QA3. CLKA Noninverting Differential Output 3. Terminate with 100 to QA3. CLKA Inverting Differential Output 2. Terminate with 100 to QA2. CLKA Noninverting Differential Output 2. Terminate with 100 to QA2. CLKA Inverting Differential Output 1. Terminate with 100 to QA1. CLKA Noninverting Differential Output 1. Terminate with 100 to QA1. CLKA Inverting Differential Output 0. Terminate with 100 to QA0. CLKA Noninverting Differential Output 0. Terminate with 100 to QA0. Exposed Pad. QFN package only. Internally connected to ground.
MAX9317/MAX9317A/MAX9317B/MAX9317C
3 4
6 7 9, 16, 25, 32 10 11 12 13 14 15 17 18 19 20 21 22 23 24 26 27 28 29 30 31 --
_______________________________________________________________________________________
5
Dual 1:5 Differential Clock Drivers with LVPECL Inputs and LVDS Outputs MAX9317/MAX9317A/MAX9317B/MAX9317C
CLK VIHD - VILD CLK tPLH tPHL VILD VIHD
Q_ VOD Q_
VOH
VOL
80% DIFFERENTIAL OUTPUT WAVEFORM
80%
Q_ - Q_
0V (DIFFERENTIAL)
20% tR
20% tF
Figure 1. MAX9317 Timing Diagram
Detailed Description
The MAX9317 family of low-skew, 1-to-5 dual differential drivers are designed for clock or data distribution. Two independent 1-to-5 splitters accept a differential input signal and reproduce it on five separate differential LVDS outputs. The output drivers are guaranteed to operate at frequencies up to 1.0GHz with the LVDS output levels conforming to the EIA/TIA-644 standard. The MAX9317/MAX9317A operate from a 2.375V to 2.625V power supply for use in 2.5V systems. The MAX9317B/MAX9317C operate from a 3.0V to 3.6V supply for 3.3V systems.
CLK_
CLK_ RIN 50 VT_ VCC 2.0V RIN 50
LVPECL DRIVER
MAX9317A MAX9317C
(a) MAX9317A/MAX9317C CONFIGURED FOR LVPECL INPUT SIGNALS.
Differential LVPECL and LVDS Input
The MAX9317 family has two input differential pairs: CLKA and CLKA, and CLKB and CLKB. Each differential input pair can be configured or terminated independently. The inputs are designed to be driven by either LVPECL or LVDS signals with a maximum differential voltage of VCC or 3.0V, whichever is less. The MAX9317A/MAX9317C reduce external component count by having the input 50 termination resistors on chip. Configure the MAX9317A/MAX9317C to receive LVPECL signals by connecting VT_ to VCC - 2V (Figure 2(a)). Leaving the V T_ input floating configures the
6
CLK_ RIN 50 VT_ RIN 50 LVDS DRIVER CLK_
MAX9317A MAX9317C
(b) MAX9317A/MAX9317C CONFIGURED FOR LVDS INPUT SIGNALS.
Figure 2. MAX9317A/MAX9317C Input Terminations
_______________________________________________________________________________________
Dual 1:5 Differential Clock Drivers with LVPECL Inputs and LVDS Outputs
respective input with a differential 100 termination to receive LVDS signals (Figure 2(b)). The MAX9317/MAX9317B accept LVPECL if the inputs are externally terminated with 50 resistors from CLKA and CLKA or CLKB and CLKB to VCC - 2V. Alternatively, if the inputs are differentially terminated with 100, they accept an LVDS input signal. The LVDS input signal must adhere to the specifications given in the Electrical Characteristics table. Note that the signal must be at least 1.2V to be a valid logic HIGH.
Circuit Board Traces
Circuit board trace layout is very important to maintain the signal integrity of high-speed differential signals. Use 50 traces for CLK_, CLK_, Q_, and Q_. Maintaining integrity is accomplished in part by reducing signal reflections and skew, and increasing common-mode noise immunity by keeping the differential traces close together. Signal reflections are caused by discontinuities in the 50 characteristic impedance of the traces. Avoid discontinuities by maintaining the distance between differential traces, and not using sharp corners or vias. Maintaining distance between the traces also increases common-mode noise immunity. Reducing signal skew is accomplished by matching the electrical length of the differential traces.
MAX9317/MAX9317A/MAX9317B/MAX9317C
Applications Information
Output Termination
Terminate the outputs with 100 across each differential pair (Q_ to Q_). Ensure that output currents do not exceed the current limits as specified in the Absolute Maximum Ratings table. Under all operating conditions, observe the device's total thermal limits.
Chip Information
TRANSISTOR COUNT: 1119 PROCESS: Bipolar
Power-Supply Bypassing
Bypass each VCC pin to ground with high-frequency surface-mount ceramic 0.1F and 0.01F capacitors in parallel and as close to the device as possible, with the 0.01F capacitor closest to the device. Use multiple parallel vias to minimize parasitic inductance and reduce power-supply bounce with high-current transients.
Pin Configurations
QA0 QA0 QA1 QA1 QA2 QA2 QA0 QA0 QA1 QA1 QA2 QA2 26 VCC VCC VCC VCC 25 24 QA3 23 QA3 22 QA4 21 QA4 20 QB0 19 QB0 18 QB1 17 QB1 9 VCC 10 QB4 11 QB4 12 QB3 13 QB3 14 QB2 15 QB2 16 VCC
TOP VIEW
TOP VIEW
32 GND N.C. (VTA) CLKA CLKA N.C. (VTB) CLKB CLKB GND 1 2 3 4 5 6 7 8 9 VCC
31
30
29
28
27
26
25 24 QA3 23 QA3 22 QA4 21 QA4 GND N.C. (VTA) CLKA CLKA N.C. (VTB) CLKB CLKB GND 1 2 3 4 5 6 7 8
32
31
30
29
28
27
MAX9317 MAX9317A MAX9317B MAX9317C
20 QB0 19 QB0 18 QB1 17 QB1
MAX9317 MAX9317A MAX9317B MAX9317C
**EXPOSED PADDLE
10 QB4
11 QB4
12 QB3
13 QB3
14 QB2
15 QB2
16 VCC
TQFP (7mm x 7mm)
( ) MAX9317A/MAX9317C.
QFN-EP**
**EXPOSED PADDLE AND CORNER PINS ARE CONNECTED TO VEE.
_______________________________________________________________________________________
7
Dual 1:5 Differential Clock Drivers with LVPECL Inputs and LVDS Outputs MAX9317/MAX9317A/MAX9317B/MAX9317C
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QFN THIN 5x5x0.8 .EPS
L
REV.
0.15 C A
D2
C L
D
b D2/2
0.10 M C A B
PIN # 1 I.D.
D/2
0.15 C B
k
PIN # 1 I.D. 0.35x45
E/2 E2/2 E (NE-1) X e
C L
E2
k L
DETAIL A
e (ND-1) X e
C L
C L
L
e 0.10 C A 0.08 C
e
C
A1 A3
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO.
21-0140
C
1 2
8
_______________________________________________________________________________________
Dual 1:5 Differential Clock Drivers with LVPECL Inputs and LVDS Outputs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX9317/MAX9317A/MAX9317B/MAX9317C
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220. 10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL DOCUMENT CONTROL NO. REV.
21-0140
C
2 2
_______________________________________________________________________________________
9
Dual 1:5 Differential Clock Drivers with LVPECL Inputs and LVDS Outputs MAX9317/MAX9317A/MAX9317B/MAX9317C
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
32L/48L,TQFP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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